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A page with some raw transscripts for the uploaded youtube videos, which can be used to simplify or summarize the video into readable wiki pages, or possibly as a source for subtitles in case a term unknown to the audience is used

Semiconductor Fabrication Basics Background Theory video[edit]

Hi, so I'm going to be making creating 3 videos, this is the first of which where I'll be covering the Semiconductor Fabrication Basics

So I'll be going through an overview of all of the steps required to make semiconductors, and then Ill be going to go a little more in depth in to each one of those, and talk about how the process works and the tools that are used to do that process

In the next video, i'm going to show you how you can do some of those processes at home, on a low budget in a non clean-room environment so basically setting up a home chip lab.

And then in the third video, I'll be going step by step in _my_ home setup, either making a diode or a transistors or maybe a NOR gate, step-by-step through that, and that's probably be a long video, and that will give you a more of a hands-on for you for all of these steps.

To make the most sense out of these video's you should already have a basic understanding of terminology like doping, p-type, n-type, charge carrier mobility, you should be familiar with wafers crystal orientation <100>, <110>,<111> and the major and minor flats associated with them. All of that you can easily find on-line if you just look up semiconductor basics and stuff like that.

OK, let's go over a quick overview of all of the steps

Right here I have a drawing on how I manufacture NMOS FETs, these are N-type metal-oxide semiconductor field effect transistors, basically n-channel MOSFETS.

And you start with a P-type <100> orientation wafer, the first step is called oxidation, this is a field oxide, and I grow on top of it a layer of silicon dioxide, SiO2, and that's basically sand or glass or whatever you want to call it, it's very very pure and it's a dielectric and its an insulator, and this is very very important, these layers are used for passivation (so protection), for insulation between multiple structures that you are building onto the wafer, and also more importantly they are used for the gate oxide of the FET here.

So the first step, I grow this insulating layer right here on top of the wafer, and I'll talk about how that's done, there's a few methods of doing that, the one that I want for a field oxide its called, this is the first thick oxide here, I want about 500nm (5000A) thick and that'll be a blueish color due to thin film interference.

The next step, I apply a mask to the wafer, and then dunk it in a hydrofluoric acid solution that then etches away these active areas into that SiO2 layer so we are left with the wafer with these regions of insulator on top of them but then these regions in between are bare silicon.

Before you etch it in HF acid, if you want to clean up the wafer a little bit more you can do a surface treatment with "piranha" sulfuric acid, hydrogen peroxide and theres also RCA clean parts 1 and 2, theres some pretty nasty chemicals in there so be you have to be very careful...

The third step is the doping, so I spin-coat a dopant and for N-type doping -I want to make these N-type wells here- that would be a phosphorous solution, so for this you can take phosphoric acid, and you can put it into water or if you want it to spin-coat even nicer you can use an alcohol solvent. Filmtronics sells pre-made spin-on diffusants and so does Emulsitone, but for both those companies its very pricey, and you can only get it in large quantities so you should get on with making your own... and you can spin-coat this by placing it on a rotating motor at around 3000RPM and you put this film onto it and it will spread across so this is one method of doping here and after thats on there you do pre-deposition and you put it in a furnace for about half an hour and it drives in the phosphorous atoms, so this is one method of doping called diffusion and it's in the past years mostly been replaced with ion implantation, other techniques, but this is the easiest way to do doping at home, so once we have N-type doped wells here, then we grow back a gate oxide, so we grow another layer of SiO2 very thin in the middle here, and then we make connections to the Drain, Source and Gate regions and the body of the MOSFET connects up to the source.

To make the masks that I was talking about up here, theres a process called photo-lithography where you take a wafer you coat it with a photosensitive paint called photo-resist, and then you put a mask on top or in proximity of the wafer, or with projection systems the mask is further away with some very complicated optics, but to keep it simple I'll say you put the mask on top of the wafer and then you expose very high intensity UV light on to that wafer with the masks on it, and the masks limits the UV light to only hitting some portions of the chip, and then once thats done if its negative resist then you have to bake it one more time, but then you develop it and then you have a patterned wafer. So that would have a layer of photo-resist on top of this with some patterns in it and then you put it into the HF acid. The photo-resist will stop the HF acid, but the HF will still be able to etch through the (unprotected) SiO2 layers underneath there. We'll come back to this same drawing here in the second video when I talk more about how I do these processes at home.

OK the first topic that I want to go in more detail about is oxidation, so I talked about this a bit before, this is the growth of an oxide layer like SiO2 on the wafer and it is used for a lot of things, its extremely useful for passivation so for a protection layer, its a hydrophilic layer and bare silicon is hydrophobic so if you want to spin coat a chemical on to this such as a dopant chemical you want the silicon to be hydrophilic and it helps to have a very very thin oxide layer that you grow onto it and that will allow the water-based dopant to spin onto it easier, and its so thin it doesn't act as a dopant barrier. When you do a RCA clean steps 1 and 2 it actually leaves a very thin SiO2 passivation layer behind, so hydrophilic is very useful however when you're spinning photo-resist onto it you want a hydrophobic surface, you want to get rid of all the water on there, so not so very good for photo-resist.

Second thing, dopant barrier, so in the previous drawings I showed you about the MOSFET fabrication we used the SiO2 layer and then etch a pattern into it and then that pattern will prevent the phosphorous atoms from diffusing into the wafer in those spots, although P atoms do diffuse through the glass and the glass will become lightly doped its much slower than the diffusion through the silicon wafer so the dopants are effectively blocked by the SiO2

And then the last 2 uses: Surface dielectric and device dielectric and this is the use in MOSFETs because the gate or any device that makes a capacitor onto a piece of silicon is using it in this manner where capacitor is basically 2 parallel plates and this is the dielectric that separates those 2 plates. Why SiO2? Well, it's easy to work with, it can be grown thermally which is very nice, one of the main goals of fabrication plants is to cut down the thermal budget so a lot of times thermal oxidation is only used in a very very large high production area when they can keep their furnaces up 24/7 and keep feeding wafers into them, at low volume runs the thermal budget starts to become overwhelming. Another reason why SiO2 is used is because its thermal expansion characteristics are very similar to that of silicon so as you put the wafer in and out of furnaces in different steps as the wafer expands and contracts the SiO2 passivation layers will expand and contract at a similar rate so that when you pull them back out of the oven nothing gets cracked or stretched and all of your CD (Critical Dimensions) stay very much the same, its not going to be perfect but its better than other passivation layers. Thermal oxidation basically means you take the wafer and put it in a really hot oven and the SiO2 will grow onto that naturally which is very nice. There's 2 methods: dry and wet. Wet is much much much faster for a couple of reasons but to know that you have to understand the mechanisms first, we'll get there. This is what's going on for dry oxidation. We're just using the ambient Oxygen O2 in the air and then that comes in contact with the silicon and this should be over a lot of heat over 1200 degrees C it starts around 900 deg C 1200 deg C is really where you want to be if you are building an oxide and that forms SiO2 so -I'll talk about the graph in a second- so a few different thicknesses here it can range normally between a 100 and 5000A is where your practical limits are but this term here saying that gate oxides are around 150A thats actually not quite true anymore we are getting at smaller and smaller and the advantage of thinning out that gate oxide is giving us a lower threshold voltage on field effect devices which is great but it gives us more and more leakage so its kind of coming to equilibrium here where we do not want to get the gate oxides much smaller, and I believe -Im not too sure about this- but I believe the aspect ratio between gate length to gate thickness is about 9, I think, Im not too sure about that, so the thinnest gates are used for tunneling devices because you'll experience quantum tunneling at these very very thin gate oxides and thats part of the reason why these very thin gate oxides on MOSFETs they experience leakage because of the tunneling effect, as we get thicker than that they are used for pad oxides on more complicated devices [for LOCOS processing], passivation is a thick layer, but the thickest layer of SiO2 that will be used is for field oxides, its called field oxides not only because they are dopant barriers, all of these are for the most part, but because it blocks electric fields, its too thick to create an electric field under most conditions, so field oxides are not used for gate oxides because they are just too thick, and gate oxides rely on the fact that the oxide can be used to create electric fields and store charge in it but field oxides are too thick and we use that to our advantage when fabricating devices because it allows us to insulate multiple FET devices and grow more metalization layers and such onto a wafer.

Now let's understand the growth mechanism real quick, so with any thermal oxidation for the oxidation to take place, the oxygen O2 molecules have to come in contact with the silicon, and at first when you have a bare silicon wafer and you stick it in the oven thats great it happens right away you know you got this oxygen plentiful and you got the silicon wafer, but then as soon as you have the first layer of silicon dioxide grow onto that wafer all the sudden you have this layer thats blocking the silicon wafer underneath from the oxygen in the air so the rate will slow down, because like I said the reaction can't take place if the oxygen molecules are not in direct contact with the silicon, now we have this SiO2 layer in between them, so for the reaction to continue, either the silicon atoms have to diffuse up through the SiO2 to get to the oxygen, or the oxygen has to diffuse down in the SiO2 to get to the silicon wafer underneath and thats what happens with thermal oxidation, so initially this is called the linear growth stage, and its defined by linear growth constant B/A times time t, and that's right here in the graph here, that happens quite quickly and quite linearly, but then right here we get into the parabolic stage and its on the graph basically an inverse slanted parabola and thats due to that first SiO2 layer growing so that the O2 molecules are no longer in direct contact with the silicon and they have to diffuse all the way through that SiO2 layer and it takes a little bit of time to do so, so that's why we get this parabolic growth area here, and that can be kind of mitigated when we get to higher and higher temperatures. So at 950C this is going to be a more pronounced parabolic growth and then at 1200C its gonna be a little bit more linear a little bit better, but to help that problem even more than just raising the temperature, we do wet oxidation, and instead of using ambient O2 atmosphere we pump steam or water vapor into the furnace, and this cuts down the time dramatically to do so. Initially the linear growth linear is not changed much, but it will help this parabolic growth region immensely, and thats because when we're dealing with dry oxidation we're waiting for this big O2 molecule to diffuse through an already formed SiO2 layer, but with wet oxidation we're starting with Si + water and thats gonna yield SiO2 + H2 gas but since we are dealing with this water vapor it's actually a hydroxyl ion and it's smaller and will actually diffuse through SiO2 much much quicker than this O2 molecule, and that allows the parabolic growth region to be subdued and mitigated more, so we have more of a linear region throughout, and that's why wet oxidation is really the way to go, especially if you are doing this at home and you don't want to wait 24 hours to grow a field oxide, you can speed things up a lot by doing wet oxidation. But let's look at the downsides real quick. A very big goal of semiconductor fabs everywhere is to decrease the use of steps that involve liquids. We want to get everything so that all of these steps are done with gas sources, because gases are very pure and easy to maintain pure, so if we are just feeding this water even if its high quality deionized distilled water into the chamber and it becomes water vapor, there's a lot of opportunities for impurities to get in there, and the SiO2 film that is grown will not be as nice and as pure and as uniform when we do wet oxidation, the nicest film is with dry oxidation. Also semiconducting devices generally decrease in performance as they're exposed to more and more oxygen throughout all of the thermal steps, so if we can limit the amount of oxygen that they are exposed to that's better generally, it's mainly in diffusion steps where thats critical. But the dry oxidation although slower and more expensive because these furnaces have to be up higher and for longer, but it does give you a much nicer oxide, now this is only an issue when we are talking about things like gate oxides, that are very small, thin, precise and can't have a single pinhole on them. Because if we have a pinhole on the gate oxide, its no longer an insulating gate device, your electric field will be all screwy and the device characteristics will basically be garbage, so dry oxidation is a very good method for making gate oxides.

OK, let's continue talking about oxidation. So one major thing that influences the rate of oxidation is the crystal orientation of the wafer that you are growing it onto. For example <111> orientation wafers have a higher packing density, they have more silicon atoms per unit volume [? area I think] so the rate of growth will be a lot faster on <111> wafers, and field effect devices are fabricated on <100> wafers so that means some of the thermal steps are slower for making field effect devices as opposed to MEMS and bipolar devices. Oxide layers that are grown over highly doped phosphorous regions are less dense, this is very important, they also etch faster thats because they are grown faster, up to five times the growth rate which is incredible so you have to be very careful of this when you are planning out oxide growth and etching steps, this also leads to higher undercutting and lots of other problems, so you think "oh!" you know "faster rate!" but sometimes thats an issue.

When we have N type regions an effect called pile-up happens, and the reverse happens with P type "depletion", this is because phosphorous, an N type dopant, has a higher solubility in silicon than it does in SiO2. As the SiO2 layer grows, we talked about earlier how it grows not only above the surface of the wafer, but also into the wafer itself, because the oxygen or hydroxyl ions are diffusing into the wafer surface, so this oxide layer grows on top of the wafer and into the wafer. As it grows into the wafer the advancing SiO2 layer, literally pushes the N type dopant atoms further and further into the wafer, and they remain at the interface between the SiO2 and the silicon, so thats pile-up. And then the reverse happens for P-type dopants, where they're actually drawn out of the wafer so both of these you have to be very careful about when you are designing a process because they can dramatically affect your dopant distribution. Another thing that affects rate is the presence of hydrochloric acid HCl, and there's actually some methods of oxidation -cooling added oxidation- that actually uses to increase the rate overall and this could also introduce a whole lot of mobile ionic contaminants and other stuff. Another thing you have to be very careful about are differential rates, because we talked about earlier the difference between the linear and parabolic growth region. So if you have a wafer, here as an example these are the steps to make a FET, some regions of SiO2 are thicker than other regions let's just say this region here is below 500A, and this one is about 2000A. this means when we put this back in the furnace to add more, this will be in the linear growth stage and this will be in the parabolic growth region, this thing will grow faster than that. So you may think "Oh! well if I have a growth rate of 1000A per hour, I put this wafer in the oven and if I take it out after one hour, everything will be a 1000A thicker!" that is far from what will actually happen, you will have a lot of variations in rates all across your wafer, because each oxide is in varying stages of this growth and thats even more expanded on the non-uniformity of it due to uneven heating while its in the furnace so theres a lot of issues there and thats partially where CMP (chemical mechanical planarization) will come into play, another extremely complicated topic, that is outside the scope of this video. Anyway you have to be careful about differential oxide growth rates. Some other processes other than this thermal oxide growth: I'm not gonna over them, but it's worth mentioning theres rapid thermal processes, theres high pressure oxidation which gets rid of a lot of the issues with thermal oxidation and then theres anodic oxidation, which I try theres a video elsewhere on my youtube channel, the problem is it involves an aqueous solution of potassium hydroxide or potassium nitrate or something, and thats very dirty, its hard to control contaminants in liquid solution, thats why a lot of semiconductor processes deal only with gases. So its very simple, basically just passing a current through - you got your silicon wafer immersed in this aqueous solution and thats connected to the positive of a current supply I use about a 100V DC on mine hence the name anodic oxidation, and then the negative just goes to the solution as a whole. And this is done at room temperature atmospheric pressure.

This is extremely brief overview of photo-lithography, people have spent there entire life studying this one process alone, so I'm not even gonna scratch the surface with this and I won't attempt to, but the basic idea of photo-lithography is patterning a wafer, so in this drawing here I have a silicon wafer, a SiO2 passivation layer on top of it, and then a photo-resist layer thats spun on top of that SiO2 layer. That photo-resist is a photosensitive paint, we then have a mask above it that blocks light in some portions and allows light to go through in other portions. Intense DUV deep ultraviolet light is passed through that masked, and the light is stopped in this section and the light continues trough in these sections. This is a negative acting photo-resist, meaning that the portions that are exposed to light become polymerized and then after they are developed they don't wash away and they become structures. So the light is blocked in this little section in the middle therefore washes away after being developed and we're left with a hole. Now photo-lithography is extremely intricate and there are techniques to expose feature sizes that are incredibly small in the tens of nanometers ranges and below and these sizes are even smaller than the wavelength of the light used to expose them its absolutely incredible. You'd expect that the masks used are very expensive and they are! The masks are made out of I believe chrome plates that are written onto directly with focused electron beam and a set of masks to make an IC is hundreds and hundreds of thousands of dollars its absolutely nuts. There's 2 different [???] of masks, theres light field and dark field (sometimes called clear field or light field) and light field masks, the majority of them is clear its transparent, and the features you want to transfer are dark, and thats what this masks up here is, and then theres dark field masks where the majority of the mask is dark and the feature you want to transfer is light and then theres 2 kinds of structure, hole and island, this is a hole and the inverse of it would be an island if this portion was polymerized and these 2 were un-polymerized. So this is just a quick thing you should be able to memorize. Theres a couple different types of photo-resist theres of course negative and positive, theres also light-sensitive and energy sensitive there are resists that are, the majority of them traditionally are UV sensitive, but theres also direct e-beam writing and writing and theres also X-ray methods for doing photo-lithography. Within the photo-resist theres 4 types of chemicals: polymer, solvent, sensitizer and sometimes additives. The polymer is the actual light-sensitive part, its the thing that changes structure, it becomes polymerized or becomes soluble based on the light that hits it, and the solvent is I don't know maybe like an alcohol or something like that, and that allows it to be coated in very thin layers onto the silicon wafer, that allows for spin coating basically, and then theres sensitizers and these are specific to the brand of photo-resist you buy I guess, and this allows the company to fine-tune the actual chemical reaction thats taking place during exposure, the method of polymerization basically, and the final thing are additives, so sometimes they'll add colored dyes into the photo-resist and other chemicals that the company desires that increase resolution capability, process yield, things like that, maybe its an additive that allows them to manufacture the photo-resist cheaper, possibly to make it have longer shelf life, possibly to focus the sensitized light region, so it only works on a specific part of the DUV spectrum, so this kind of thing would be additives inside the photo-resist. As far as characteristics of photo-resist, because you might think that negative and positive photo-resist are basically interchangeable but you just have to change your masks, thats not the case at all, negative and positive photo-resist are extremely different. Using positive photo-resist will give you higher resolution, higher aspect ratio, aspect ratio is the ratio between the smallest feature you can make and the thickness of the spin-on photo-resist. So positive wins in that category, but negative is easier to apply, has better adhesion, and negative also has a faster exposure speed, so you can run through an automated process faster and faster so negative is kind of better in those respects and is easier to work with. Positive same trend with the resolution, higher resolution, also higher quality, lower pinhole and impurity count, positive will flow into small steps into SiO2 and stuff much easier and it gives you better coverage in that respect, but positive is also more expensive, as far as removing the photo-resist after its been developed positive can be removed with simple solvents, some are water soluble, some alcohols and stuff. And the negative generally you need chlorinated substances, more nasty acids and stuff like that. The photo-resist strippers for negative are a little bit more nasty.

Photo-resist is normally spin-coated onto the wafer, so there'll be a vacuum chuck where the wafer will be placed onto the chuck and a vacuum will suck it down onto the platform so its nice and flat, and then theres either static or dynamic dispense, where an arm will come across and dispense the photo-resist either when it is static when the wafer is not spinning, or dynamic the wafer will start spinning and then dispense, and then spin up to a higher RPM normally in the 3000-5000 RPM range and that will make a nice even coating of the photo-resist right across the wafer, and then the excess will fly off and -its not recycled of course- but it will fly off and be collected. Before the photo-resist is spun on, theres a number of surface treatments that take place mainly just to get rid of all the water on this, theres dehydration baking, RCA cleans and stuff like that are not really used prior to this because they allow a hydrophilic surface, but I believe like an HF bath would make sense, because if theres no previous steps that would be screwed up by that, an HF bath would leave a nice hydrophobic surface for the photo-resist to be applied onto, then it will be spun, it will be dried, depending on if its negative or not there might be another soft-bake or hard-bake step and developed and dried.

Aright lets talk about alignment and exposure techniques: So the first exposure techniques were basically contact, and thats where the mask on top was lowered down so it was touching the surface of the wafer, UV light was exposed through, and that was your exposure, and theres a couple of issues associated with that one of which is since you actually have a physical connection between your mask and your wafer, transfer of contamination, the mask does not last as long, you can scratch up the surface of the wafer, things like that, that lent to the development of proximity exposure systems where the mask is lifted off the wafer by a very small gap in between them, so the mask and wafer are in very close proximity, that eliminates some of the problems with contact, but as we get to smaller and smaller feature sizes, that little gap between the mask and the surface of the wafer really degrades the actual resolution that we can get, you know there's some diffraction, and some of the light is not passed through that gap as it should be, some of the light is set there off at different angles, and the image can be skewed so your critical dimensions are not quite what you wanted them to be. Next we have projection and stepper, stepper is the most complicated optical setup basically, and these use reticles or masks and projection systems so that the light source is further away from the wafer, its basically similar to - it's a reverse enlarger if you ever worked in a dark room developing black and white photographs, it's the opposite idea of an enlarger. So you have a light source and then right below it you have your mask, and then you have focusing lenses that focus that down and then you have your chip that gets exposed, a piece of silicon and then a stepper can do very high quality images, the mask contains the image for one chip, and that gets focused down onto an entire wafer, and then the wafer is stepped so that that image for one of the chips is exposed onto multiple locations on the wafer, and then the whole wafer is filled up with that exposed image onto it. So these ones right here are optical exposure methods, and then theres energy or non-optical exposure methods right here, these are done in vacuum, or at least e-beam is. so depending on the photoresist, some are sensitive to x-rays and e-beams, cool thing you can do with electron beam is that's actually a direct writing method where no mask is used, and where you have a very focusable and finely deflectable electron beam you can use that to write directly on the photoresist surface, it's just like a CRT it's like a raster scan and it wil draw out the image with this e-beam, I think it has to go over the image a few times to get it actually burnt into that photo-resist.

OK, let's talk about doping next. So I'm gonna start with diffusion, which is a very simple method of doping, it has some downsides which I'll talk about in a second, it's commonly done inside a tube surface, and it's basically you're driving in atoms of phosphorous, arsenic or boron or whatever your dopant material is using a lot of heat. So the steps to do this, these are the steps to do it with a liquid source, theres liquid source, gas source and solid source. Solid source you have to use like BOCl3, gas source you gonna have diborane and phosphene gas, and they pump it in a chamber where the diffusion takes place. But with liquid source the steps we take to do that is: first we clean the wafer and if you etch it with HF after you clean it, you're going to want to put a very thin layer of SiO2 onto it so you have a hydrophilic surface and the next step will go nicely, if you have a hydrophobic surface caused by the HF then you won't be able to spin-coat the wafer very easily, it will bead up and it won't go well, so I recommend if you have to do an HF step right before it, do that and then do the first part of the RCA clean or something like that to leave a small passivation layer, then the next step you are going to put a couple of drops of either a phosphouric acid or boric acid solution depending on if you are doing you know N-type or P-type doping, and you're going to spin-coat that onto your wafer, and then right after you do that you don't want to leave it on the wafer too long before you do the pre-deposition step because you can get like hazing and things like that because of the excess oxygen thats going to come into play here. The next step known as predeposition places a high concentration of the heavier phosphorous or boron atoms and they come out of the acid and it places them right over the area where you want to do the diffusion and this can be done on a hot plate where you just place your wafer on top of the hotplate on like a piece of tin foil or something on a couple of hundred degrees C for 15 minutes or so or it can be done up to a thousand degrees C very quickly I'm sure theres also a rapid thermal process for doing this. After you do that you'll notice that on top of the wafer there's a thin, it will be thick actually, oxide layer that will form because your phosphorous spin on source is basically acting as a spin-on glass, and after the predeposition that will form glass on it, so you can put that in a weak HF bath maybe 1 or 2 percent, that will get rid of all the excess phosphorous film and also that unwanted oxidation on top of it. Then you'll do your drive-in step, and this takes place at 1200deg C optimally, it can start as low as 950 degrees C but you really want 1200 degrees C for about 45 minutes, and you want a very nitrogen rich atmosphere to do this drive-in diffusion step in. Once you take it out of the furnace, we talked earlier about depletion and pile-up, anytime you put this wafer in a furnace there's going to be some oxidation, whether you want it or you don't and that oxidation is going to change your distribution of dopants, so you have to be careful about that, so these graphs they indicate that at the surface here on an N-type diffused wafer will have a very high doping concentration as we progress that will drop of quite steeply because of the pile-up and then decrease after that. But then on the surface of a P-type wafer, it's depleted of those P-type charge carriers because of the depletion mechanism. One mostly unwanted side-effect of the diffusion is lateral diffusion, because ideally if we wanted to create a N- or P-type well right here, the atoms would diffuse straight down, and that would be awesome, but they don't, they diffuse to the sides, as much as they diffuse straight down, this is normally unwanted and this is one of the main reasons for the ion implantation technology being developed, which I will talk about in a second. There are some devices that actually use this to their advantage, there are LDMOS transistors, laterally diffused metal oxide semiconductor field effect transistors, and those use lateral diffusion to I believe they use it in like high power RF applications, microwave RF applications, and it allows them to put higher voltages through the device of this RF energy, they can put higher voltages before breakdown occurs, which is interesting.

That pre-deposition step, you better look at that, once we spin on the film on top of it right here, then that pre-deposition step will put a high concentration in this case of phosphorous atoms right here, and right here and then they are driven in to create these N-type wells.

This is the datasheet for emulsitone dopant this is for Borofilm 100 what they call it, and it says in here, well this you could basically assume, at higher temperatures you're going to have a lower sheet resistance at the end, and the same with longer times [???] but more importantly if we look at the atmosphere if you do this in ambient atmosphere so what's that you know like 70% nitrogen 20% oxygen so thats close to right here, thats the sheet resistance we're gonna have across the wafer, but if we do it in a purely nitrogen atmosphere, which it's done close to that commercially in a fab they'll pump nitrogen through it, we can decrease the overal sheet resistivity which is great, so it's very easy to create an atmosphere inside of a tube furnace, which is what these steps are normally done in, you basically just blow the nitrogen into the furnace, either perpendicularly or parallel to the wafers themselves, I think in here it says perpendicularly is best, but depending on what material you're blowing it, it differs. So the more nitrogen you have during the diffusion step, the better electrical characteristics you can get at the end.

Last thing I want to talk about under doping is ion implantation, which is a incredibly complicated and dangerous and expensive and massive technology which eliminates this lateral diffusion issue, it also allows for extremely precise control over the distribution of the dopants, not onl the depth but also their concentration at that given depth. To explain that I'm gonna go to a book that has some better drawings than I could do, this is "Microchip fabrication" by Peter Van Zant, so here is your typical ion implantation system. First it's got an ion source, so there'll be phosphene or diborane gas that will come in here, it will be ionized into a plasma state, and then that will be electrostatically focused into a beam, and there's a mass analyzing magnet, and these are typically 90 degrees, somewhere a little bit more than 90 degrees, and this is set-up so that you can select which ions you want to implant, the ions that are heavier than what you want will not be able to make this sharp turn along the magnet and will hit the wall, the ions that are heavier [lighter?] will go too far and smash into the other side of the wall, and the ions that are just the right weight of what you want will make the 90 degree bend and go straight through, and then they're accelerated electrostatically and there's some magnetic lenses and such that give you a nice focusable and deflectable beam, and these super high energy ion beams can be in the MeV range and these machines are massive, then this focused beam can be scanned across your wafer in a raster scan style so that it can implant these ions into the wafer very uniformly. This is the mass analyzing magnet I was talking about, so we can select what ions we want based on their weight. This is how electrostatic beam deflection works, we can choose between ions that we want and other gasses that are not charged by passing them through electrostatic plates like this, and we can deflect only the ions into a wafer that we're implanting and then the other random gases that are impurities will continue straight across and be unaffected, and those can be trapped somewhere else and extracted. And this is the beam scanning I was talking about, so that we can coat the entire wafer and implant these ions.

Ion implantation can also be used to very precisely control and modify threshold voltages of field effect devices like a MOSFET and can also be used to implant isolation slots, this is typically used in Gallium Arsenide high electron mobility field effect transistors so for microwave applications

OK, the last 2 topics to talk about in this video. So everything up to this point has talked about how to make discrete devices, so how to make a single transistor, how to make a diode, something like that, but the difference between the ability to make discrete devices and actual integrated circuits is metalization, metalization allows us to make small connections between individual transistors that are on a board and connect them in ways that they have a greater function than just being individual transistors, so metalization is done by taking a wafer that has all these transistors and everything on it already, and then the entire wafer surface will be coated with metal, aluminum or copper something like that, and then same as photo-lithography process will happen, and then we can etch away that metal just to leave little traces and connections that connect all these individual components on the board. There's a few ways of doing that, enter the big umbrella of deposition, thin film deposition. There's so many methods that you can research, mainly there's chemical vapor deposition CVD, and physical vapor deposition PVD. So there are lots of CVD techniques, but mainly they are used to deposit and grow insulators and semiconductors, out of the insulators you can do SiO2 and silicon nitride layers, and out of the semiconductors you can grow epitaxial silicon, also polysilicon as well. Evaporation is a PVD technique and it can be used to deposit conductive metalization layers, like aluminum, copper, gold, nichrome, probably like tungsten if you have enough heat to be able to do that. Sputtering is another PVD technique, you can actually sputter SiO2 interestingly enough, but mainly its used to coat metals, like tungsten, titanium, molybden, aluminum, a huge use for sputtering is ITO, Indium Tin Oxide, you can create clear conductive coatings, and these are used heavily in organic LED technologies and thin film displays, things like that. Molecular beam epitaxy is kind of chemical process but its considered a PVD technique, MBE can be used to do so much stuff its incredible, mainly its used to do complex semiconductors like GaAs devices, set-up with effusion cells that have a small super pure sample of whatever you're trying to deposit wheither its aluminum, silicon, arsenic, gallium and a very pure sample of that is heated up with electron beam, and it basically boils in a vacuum, that can be deposited onto your substrate very nicely.

Last topic is etching, so I mentioned earlier that you can etch SiO2 layers and stuff with HF acid, but this actually leads to something called isotropic etching, the HF solution will etch sideways in unwanted direction as fast as it etches down in the wanted direction, so ideally you want anisotropic etching, but thats not the case with these liquid etching sources. So this is why ion beam etching and milling and plasma etching has come into play, so you can actually get anisotropic etching. This is not a problem where you are making large devices, but as soon as you try to get things smaller and smaller you have to be very careful of your critical dimensions, and you have to allow for this tolerancing, another thing is every time you put your wafer in the furnace, your dopants will laterally diffuse as well, so you have to take into account unwanted lateral diffusion, and isotropic etching when you're designing a device. And you may think "Oh! I can make a .1 micron device!", well... make sure you take this into consideration, because theres a lot of wasted space in chips, especially older chips before plasma etching and stuff was very common, there was a lot of space that was wasted because of isotropic etching and such. A way around that to get a more anisotropic etch, is something like a reactive ion etching machine, so it consists of a vacuum chamber and mass flow controller where we can put a precise amount of reactive gas inside of it. and then we have this platform down here, which is sometimes spinning -not very fast I think- and thats grounded, and then we have an electrode in the top which ionizes the reactive gas into a plasma, and thats high energy RF, normally at 13.56MHz -the specific reason for using that is just because it's ISM band, and the harmonics don't screw with other electronics and stuff- and that RF excites and ignites the plasma, and it allows you to do a very controlled etch that's more anisotropic. This is a reactive ion etching machine, even more anisotropic than this would be an ion milling machine, is even more directional and better.

That's it for this video, I hope you enjoyed it and learned something, so I'll see you in the next video that I make which as I said before will be me explaining how we can do some of these steps at home, kind of improvising them and on a pretty low budget as well, and then the video after that will be an actual step-by-step demonstration of making transistors and stuff!

Home chip lab tour video[edit]

OK, this is part 2 in the Home Semiconductor Fabrication video series, if you haven't seen the first video already, go ahead and watch that, I talked about semiconductor fabrication basics, about all the processes, and then in this video I'm going to show you around my home chip lab, and give you an idea of how you can set up your own, and do some of these processes by yourself, and then in the next video we will go step-by-step through making either a diode or a transistor or something like that.

So this bench here I have set up with most of my wafer handling and semiconductor fabrication stuff, so these are just some tweezers and stuff, these are wafer tweezers, all stainless steel, and then some plastic teflon tweezers, this is what I'm using for my spin-coating right now, it's far from ideal but it's muffin [??] fan from a computer, I clipped all the blades off of it and then I 3d printed this dish, and then I use this tape to hold my wafer down, and this is a power supply, on the back I have a little board I made, and that gets us very close to 3500 RPM just so I have it somewhat consistent each time.

And I have an illuminator setup with the fiberoptic cold light coupling thing so I can see my work.

These are just some chemistry things, this is a hotplate, and this is a 3d rotator/mixer.

These are some wafer pieces, this one here has a 5000 A SiO2 layer on it, thats why it appears blue, that's a field oxide for fabricating field effect devices. These are some other wafers and pieces that I have cleaved up, this is a half [??] inch wafer here.

These are some of the chemicals that are used during the process: This is HF acid 2.3% and 1.15%, using that for etching SiO2, Two DI water baths, And then some dopants, phosphoric acid solution H3PO4 5% and ? % And in ISOpropyl alcohol and water, things like that...

Couple of furnaces, that one and the one right there, are not quite ideal for diffusion, but I can fit entire wafers, without cleaving them up, so these are great for doing oxide growth, it gets pretty hot, about 1000 degrees C to do oxide growth and stuff like that, like this 2 inch wafer here, I did that in this furnace here. And it's got a vent port in the top, I have a thermocouple going in there now, and that's great I can do nitrogen purges and get temperature readings, and I can make other atmospheres inside of this one.

This is a nitrogen tank, I use that during diffusion, it's not completely necessary, for proof of concept devices, but it really helps out electrical characteristics if you can purge nitrogen through the furnace while you're doing diffusion, and then this thing, about the same temperature as the other one just smaller, but I don't have a [courts goat?!] or anything to put the wafer on so it gets dirty,,,

And this is really what you want for diffusion, this is a tube furnace, so this is a quartz tube here, this is a 1 inch diameter, I got this made from a company called great glass, there's a few options online about $35, and that closes like that, you can put your wafers in there, and you push them with a stainless steel rod, about halfway in the middle, and this thing goes up to 1400 degrees C got this I think like a 100 bucks or so on ebay it wasn't bad, this is great for doing diffusion stuff, it hits it very quickly, it's not the nicest condition, it's got some rust and oxidation on it, but it does the job.

Some lab supplies and stuff, these are wafer pieces, this is a large 6" wafer, it's got a copper layer on it. These are some of the deviecs that I fabricated, these are diodes, photovoltaics stuff like that, and then here are some MOSFETs, the red little layer in the middle is the Gate, and and there's two like blueish green on either side of it, that's the Source and Drain, and there's the substrate connection on the back. I'm just using conductive silver epoxy to make these connections because I don't have a wire bonding machine... as of now :)

And here's the process to make MOSFETs and that's the process to make planar diodes or solar cells, you can make solar cells by making connections to either side of the wafer as well, but it's a cleaner setup, you can do it without the SiO2 layer, if you do the nonplanar method.

So this is really -on this bench here- is most of what's required to make your own transistors and stuff like that in a home environment.

And then over here, is some more semiconductor related stuff, there's a curve tracer down there, in that box I have a couple of photo-resists and their developers, just sort of chemistry stuff like lab supplies, these bottles are great for storing photoresist in, this is vinyl, like sticky carved sign vinyl, and I cut this and I can use it to mask the active areas so I can etch the SiO2 layer, I use this as a mask, I got that on Amazon, gloves super important! And up here I have my wafers, so I think, yes: 25 4" N-type wafers, this is an empty carrier, and then these are 25 each so 50 P-type 2" wafers here, I've used a few of them, you can pick this up on ebay or surplus places, but all the experiments I've done so far have used only 3 wafers so far out of my first 25, and I have a sealed lot of 25 and then 25 4" wafers all in pretty good shape, as far as substrate as of now.

This is ammonium hydroxide NH4OH, that's good for cleaning things, I use that for preparing surfaces for photo-resist, because when you apply photo-resist you want a completely hydrophobic surface, and you want to do graduation baking and all that good stuff, so when you are preparing stuff for good photo-resist adhesion, it's great to use ammonium hydroxide, you want to stay away from rubbing alcohol.

These are some photo-lithography tests, this is like a copper PCB material, and then this is on a silicon wafer, it says "<my last name>" and then "semicon 2016" that was one of the first ones, that is why it looks pretty bad, oh I actually exposed that using a DLP projector, so that's a maskless photolithography method, and same with this test pattern here, this test pattern is just in the developed photoresist it's not actually etched into the copper it's why the contrast is pretty weak, the linewidth on this one -there's some other features there you can't really see- there's the word "test" off of my finger right there, and the smallest test is 25 micron linewidth and the largest test is 75 micron linewidth, so pretty big in the [view of things?]

Over here, I have thin film deposition stuff, RF source for plasma cleaning and stuff, working on the vacuum chamber, this is a National Instruments USB6009 DAC I'm using to build a controller for the vacuum chamber, over here a hot cathode ionization gauge controller, a watt meter, a resonating quartz thickness meter, so I get live in real-time as I'm making film the thickness and rate of those films, and a variac to control the thermal evaporation [boat?]

Vacuum stuff: that's a [gated?] vapor trap, [varian navigator] 141 turbomolecular pump, some flanges and other high vacuum related stuff.

Couple of microscopes for semiconductor work, that's a Nikon right there, and it's got this awesome readout here, that tell's me stage movement down to a micron, which is pretty sweet it's a great scope.

And this is a stereozoom.

Curve tracer.

And this is where I keep most of the chemicals, or at least the acids involved with semiconductor manufacturing, So there's hydrochloric HCl, This is boric acid and phosphoric acid, these are my main dopants here, that I use for the semiconductors, Photo-resist developer, The hydrofluoric acid I get of course from the classic rust stain remover, And some other stuff HCl 37$, sulphuric acid H2SO4 I use that for piranha clean, This is potassium nitrate solution (stump remover) I can use that for anodic oxidation of silicon. And sulfuric acid, and RCA clean parts 1 and 2 those are in H2O2 solution.

Here's the vacuum chamber, so right now I'm getting this ready to do thermal evaporation of aluminum, and I will be using that aluminum to do metalization of wafers, and then I can pattern that with my photo-lithography setup -which I will show you in a second- and then I'll be able to make IC's from that.

So that's the chamber, big ISO 500ish on the top, nice big viewport, ISO 200 viewport right here, so I have plenty of viewing angles which is awesome, mechanical pump is a rotary vane its a Edwards number 12, and then I'm mounting that turbopump on that 6" [???flat] right there, on this side valve [bear trump?!] pressure transducer, it's gonna be a low vacuum gauge, it starts at 1 torr and it doesn't really go much below 0.001 torr abd then this is my high vacuum this is a hot cathode ionization gauge, a four pin electrical feedthrough, vent valve for vacuum, I need to get this thing blocked off here, couple ... there's three 2.75" [???flats] this is a thermocouple gauge here, and thats going to be mid-vacuum gauge, NPT threads, so I had to make that adapter plate basically, and then this is a 6" [con?]flat, I'm taking that off, and then I'm getting a 90degree elbow that goes 6" [cong]flat to ISO 100, and I'm gonna hang my turbomolecular pump which is over on that table, I'm gonna hang it off right here, and that's gonna be backed of course, with the [oil infusion?] pump. Down here, there is a UPS power supply, that is a 800 amp rewound microwave oven transformer and that's attached to these big 1 gauge welding cables that goes into these massive electrical feedthroughs in the bottom, and it lets me get that current into the chamber so I can do thermal evaporation, and those are the 2 electrodes right there, thats the thermocouple that right there, and on the bottom here is a controller I'm working on for this stuff, that's the front of it, it's basically a computer in it, and some power supply stuff, it runs LabView, Windows 7 with LabView running on it, and this DACQ board is going to go in there and it's gonna read pressures for my 3 pressure gauges, thermocouple readings, backing pressure as well, I have 2 massflow controllers on here, so I'm gonna be able to control my atmosphere in this so I can do plasma cleaning, plasma etching, reactive ion etching, sputtering maybe, you know all that good stuff, so that's gonna be really a lot of fun playing with that, so that's basically all of my home semiconductor setup, I have been accumulating all of this stuff and all the stuff on the table over there since like Octobre, its February right now, still have a long ways to go.

This is how I'm patterning my photo-resist, it's a not even 720p DLP projector, and it's on this mount so I can point it straight down, I put my substrate with the coated photo-resist underneath this here, this modified optics so I can focus to a half inch by half inch square piece, and then I can focus down with that a linewidth about 50micron, and then if I focus down to a quarter inch by quarter inch image, I can get down -with this projector from 1999- I can get down to 25micron linewidth pretty consistently, so that's awesome, with a newer DLP projector, if I wanted to spend a few thousand dollars, theoretically I could go past 10micron feature size, which is awesome for a maskless photo-lithography method like this.

So anyway, that's my semiconductor fabrication setup, and I haven't seen many people online or at all trying to do this kind of stuff, so it'd be really cool if other people wanted to get into this, and start making their own diodes, PN-junctions, transistors, stuff like that, I'm going to keep posting youtube videos as I make progress, trying to make integrated circuits on my youtube channel here, so stay tuned for that, and keep an eye out for the 3rd video in this series where I attempt to make a transistor, you know I'm not sure if that'll work, it may work, or it may not work, and if it does that's great and if it doesn't then we'll have a fun time looking at it and trying to figure out what went wrong with the fabrication of that, so .. thanks for watching!

DIY Homemade NMOS FET MOSFET Transistor step by step[edit]

Allright, this is the third video in my homemade semiconductor fabrication video series, if you haven't seen the first two, please go ahead and watch those, in the first one I talked about the basics of the processes, and in the second one I show you around my home chip lab and explain the processes a little bit better about how that can be done at home, and then in this video I'm going to attempt to make an N-channel insulated gate field effect transistor, commonly known as MOSFET, this is going to be an N-channel enhancement mode MOSFET.

So, before I tell you about the process and actually start doing it, please keep in mind that if you'd like to try this by yourself, you're doing so at your own risk, and it's extremely dangerous, it's extremely hazardous, there's a lot of flammable and toxic and hazardous materials you'll be working with, there's a lot of strong acids, you'll have to be working with hydrofluoric acid, high-temperature ovens, and there's a lot of hazards involved with this, so _please_ do not attempt to do this until you really understand all the processes and can be very careful and thoughtful about your safety gear as well, when you are dealing with these acids, you should be wearing full protection gear: goggles, you should be wearing not only thin nitrile gloves but actual thick chemical-resistant gloves that are resistant to the specific acids you're working with, it's extremely important.

So with that being said, we'll quickly go over the fabrication steps to make a MOSFET:

  • we're gonna start with a piece of silicon wafer, it's gonna be P-type with a crystal orientation of <100>, and we're gonna put that in the furnace, and we're gonna grow a 5000A which is 500nm thick silicon dioxide layer, and this is called a field oxide, it's a dielectric and it's an insulator, and we're going to etch and build the rest of our stuff onto this layer, so we grow that field oxide, it'll take about 2 hours to do so, and you'll know you got to the right thickness when it's a blueish color, you can look up online, there's SiO2 color charts, and it will tell you the color versus the thickness, the color is due to thin film interference, and the colour patter repeats itself, so you have to know roughly how much time it has been in the furnace for, and you can use an online calculator to figure out which region of the repeating color you're in and therefore you can get that color (thickness), I'll show you that chart in a minute here...
  • and then you can use either electrical tape, or vinyl mask, or you can spin photo-resist and expose it, but you're going to have to mask off portions, and then immerse this entire wafer in hydrofluoric acid solution, so you can etch away these windows into the wafer, and then once that's done, before you do the doping step, to make your phosphourous containing film spin onto the wafer easier, you might want to do the RCA cleans and/or piranha etch, sulphuric acid and stuff like that, because you want a hydrophilic surface, so that the phosphorous containing film will evenly spin-coat much easier, it's the reverse as if you're applying a photo-resist to it, and then after you do those RCA cleans, you don't want to do another HF step until the doping is complete
  • so once you have a nice prepared surface wafer that looks like this, then you can spin on a dopant, so we want an N-type dopant, because it's a P-type wafer, and we're going to be creating these N-type wells. For this dopant you can use a about 5% by mass phosphouric acid solution, you can put that phosphouric acid in water, isopropyl alcohol (IPA), ethanol, you can experiment with the different solvents to figure out what spins on best for you, the other options: you can buy a commercial spin-on diffusant, Filmtronics sells one and so does Emulsitone, they're rather expensive though, in this video I'm going to be using P509 phosphourous dopant from Filmtronics, and I'll go get that out of my fridge in a little bit (you have to store it at low temperatures so that it has a longer shelf life).
  • So you spin on that coating onto your wafer, and then you put it onto a hotplate, and that'll bake away the solvents, and that will put a high concentration of the phosphourous atoms, right above that N-type well, and then we put it into a furnace, at over a 1000 deg C for 45 minutes to an hour, and that will not only grow back a small oxide layer over these regions, but it will make N-type diffusion well's right there and there, so we get 2 PN-junctions and then we have a thin gate oxide, well it's a thick gate oxide
  • and then in the next step we're going to etch that down, and then grow it back, very thin, and normally I found the succesful devices mainly with red to blueish gate oxide, you don't want it too thin because you'll risk getting pin-holes and other impurities in that gate oxide, and also if you have it too thick then electric fields won't be able to be created onto that layer, and the field effect device will not work.
  • after you have that gate oxide you're going to etch two more holes to these N-type regions here and then use silver conductive epoxy to make connections to the gate, drain and source as well as one more connection onto the back side of the wafer, and that's going to be your bulk or substrate connection that's tied into the source.

Before we continue, I will take the phosphorous containing dopant film out of my fridge here, it is important that you keep it at low temperatures, so that you can increase the shelf life of it, if you leave it outside in an ambient temperature all the time it won't last you more than a few months. You're supposed to take it out about 5 or 6 hours before you're going to use it so it can come up to room temperature.

First thing you'll need to do is to grow a 5000A thick layer of SiO2 onto a P-type wafer, if you'd like to make a P-type MOSFET you're going to also use an N-type substrate, now I have already done grown this SiO2 layer since it can take many hours, this wafer here has a blueish tint to it when viewed under the correct lighting, and that indicates that it's the thickness that we want, you can print out a number of these charts online, I know that it was in the furnace for about two and a half hours, which puts it in this range, because I was pumping steam into the furnace at the time, since it's in this range we look for where the blue is, and it's approximately 500nm or a little bit above, that's 5000 Angstroms, and we're in good shape, anywhere between 5000 to 7500A is normally allright for a field oxide, you can go a little bit lower or a little bit higher.

Now I'm going to cleave this up into some smaller pieces, and then we'll be able to do some masking and etching and fit them into the 1" tube diffusion furnace. Maybe you can get a better view now of the color, with the fluorescent light that's reflecting off of it. Yeah, it's hard to see. I'm going to use a pair of stainless steel tweezers to cleave the wafer, and this plastic one just to hold it down. *click*click* :) Yeah, and occasionally bad stress fractures will occur and it won't break right across the lattice line, you can avoid that by using sharper tools, it's not really a precision process. This kind of bad cleaving is actually more likely to happen after you do this first high temperature oxidation step because it causes a lot of dislocations and other kind of fractures within the crystal structure of the silicon. So I'm going to break this up a little bit more into a couple of smaller roughly square pieces. And that's what we'll use to fabricate the devices.

Now that I have a roughly square-ish rectangular piece of wafer that has that field oxide growth onto it, I'm going to use the vinyl masks and HF etching solution to create these active areas as such here. This is a piece of the vinyl mask, and we're basically making a dopant barrier so that the region underneath the gate remains P-type and then we create N-type wells to the right and to the left of the gate. So the thickness that I cut the vinyl at will determine the width of the gate.

Going to make sure that it's completely adhered down, and there we go. We don't want to let any little molecules of the HF underneath there, because then our gate won't be properly etched. OK, cool!

Now I'm going to grab an about 2% HF solution, and then a couple of water baths. And make sure you're wearing complete safety, goggles, and chemical resistant gown, and ou should be wearing much thicker gloves than these, you also shouldn't have any skin showing. So I now have the wafer with the vinyl mask into the HF solution, and I'm going to let that etch for a few minutes, you'll know when you've etched completely through the SiO2 layer when you can take this out and put it under water, and the water will bead up and it won't wet across, because bare unoxidized surface of silicon is highly hydrophobic, so if you have a surface that will wet across with water and is hydrophilic, then you know there is still some oxide layer present onto that, and we want to get all the way through that oxide layer, except for in the part where we have masked off. And there is also a visual check, I can see that there is still a little bit of a blue tint, so we're going to leave it back in the HF here, and to speed up the process you could warm up this solution of HF, even with your hands, or on a hotplate if I didn't have it in a plastic container. The etching of SiO2 with HF acid is endothermic, so if we can add heat it will favor the right side of the reaction and the shift to equilibrium will basically occur faster. OK, that's been long enough, now I'm going to put it into, being careful it doesn't drip, and we're going to put it into the first waterbath and in the second waterbath the water-level is higher on it, so it'll rinse off any excess HF that's left up onto this tweezer here. And now the source and drain regions are no longer tinted blue, I made the gate region actually a little bit too thick, if I did this again, I would make it probably about half that, maybe a little more than half that width. Now I'm going to dry it off with nitrogen, dry off the back side too. I don't know if you can see, but the water was wetting right across of it, right across the surface without beading up, so it got rid of that whole oxide layer. Now I'm going to peel off our mask, that vinyl mask, and we'll see that the region underneath it is still tinted blue.

Now I'm going to clean that in a very dilute HF solution 0.5%, and do a very quick dunk of it in there, you can see that the middle region still has the insulating layer on it.

Now we're going to dope the wafer, so prepare your spin-on dopant, you should let it sit for at least 5 or 6 hours, so that it's warmed up to room temperature, and then get the pipette ready, so we can put the wafer onto our spin-coater here, which has some new tape onto it so that the wafer will stick to it, and we're going to spin that at 3500 RPM for about 30 seconds, and then we want to be able to put it on a hotplate here very quickly after that, if we leave the wafer on the spin-coater then the film will turn white and hazy, and the film quality will not be very nice. So we want to get it off of that without wasting much time, and get it onto an already heated up hotplate, we want to put it onto the hotplate when its about 115 degrees C, and then let the hotplate come up to about 220 degrees C, leave it there for 15 minutes and then we should see the thin-film interference colour become consistent milky white-ish, on top of this, and that means that our doped oxide layer - our phosphourous [silicon/silicate] glass layer has completely formed, and the solvents have evaporated, and then we're ready to take it off of that and then we can do diffusion steps. So the hotplate is very hot about 330 deg F, and we're going to put this onto the spin-coater, put a couple of drops of the dopant on, spin it and then we'll do the predeposition step on a hotplate. Before I do that I'm actually going to do a very quick clean of this wafer.

OK, it's been about 15 minutes, and you'll notice that the phosphorous silicate glass layer that we just made has hardened and the solvents have been driven off, and you'll also see that the interference patterns on it are not very consistent (the colors vary) and theres a region in the bottom right of this image right here that's not coated by the oxide layer that we just made, so what I'm going to do is I'm going to strip this off with HF acid, and then I'm going to redo the spin-on dopant application, but before I do that I'm going to do a Piranha clean, and that's going to allow for a more hydrophobic surface and hopefully I'll get better coverage the second time. I'm not going to show that on camera because I already showed you this process, but I'm going to do that and then we can go ahead and do the diffusion. Now before you do diffusion you can actually get rid of this phosphorous silicate glass layer, by putting it in dilute (like 1% or 2%) HF for about 30 seconds, now you can get rid of this layer completely and put it into the diffusion furnace, and your N-wells will still form and get diffused, but I'm going to leave it on, it's not completely necessary to do that step with all spin-on dopants.

We're getting ready to do the diffusion, so I have my furnace here warmed up to about 1000 degrees C, and that's going to warm up a little bit more to about 1200 degrees C, and I'm going to cap it there, I don't want my quartz tube to be completely destroyed. So I'm going to grab the wafer in a second here, and then put it in the mouth of the furnace and let it stay there for another 5 minutes, and that'll make the rest of the solvents boil off, and get rid of all the solvents in there, and then I'm going to use this stainless steel rod, and gently push the wafer into the middle of the furnace, where it's the hottest, and then leave it there for about 45 minutes, and that's the diffusion, I'm also going to take the nozzle from that yellow nitrogen tank and position it so that it's blowing a small amount of nitrogen through this furnace, and that will allow for a lower resistivity of the silicon wafer once we are done with this and overall will give us better electrical characteristics, so that nitrogen is basically replacing the oxygen, so normally we have 20% oxygen, 70% nitrogen. So we are increasing that nitrogent content quite a lot, which is great. So I'm going to grab the wafer and we'll go ahead and do that.

I forgot to mention when you are doing the field oxide step, to make the oxide grow faster you can pump steam into the chamber. there's a few ways of doing that, for that furnace back there I have the access port on the top, so I would actually drip water into that and it will instantly vaporize and create water vapor atmosphere inside of that furnace. For this tube furnace, you can have a steamer for like fabrics and curtain you can blow it through the chamber along with the nitrogen gas flow. An alternative way that works allright is to take a water bottle or graduated cylinder and then put a paper towel into it, and put it very close to the opening of the furnace and it will wick and draw that water in, and the moisture content will be a lot higher in the furnace. Now I'm doing this during the diffusion step so that it grows a small or thin oxide layer on top of our N-type wells here, while it's doing the diffusion, and the reason why I'm doing that is because later it allows me to etch small windows into that oxide and it allows me to be more precise about where I connect my drain and source electrodes to on the bulk of the wafer. (also helps prevent junction shorts)

45 minutes has passed, and I took the wafer out of the furnace, there it is. So I'm going to dip it in HF just to clean off that layer you were seeing and then I'm going to do another mask, it's going to consist of two strips of vinyl, and it's going to allow me to etch away this gate oxide here, so that we don't touch this region or that region, but we etch away the gate oxide, and then we're going to regrow it about 500 to 1000A, thats about as thin as we can go with this dirty environment without risking pin-holes and things like that, the thinner the gate oxide, the lower the treshold voltage which is great.

I created the mask just like I described, and I'm going to etch that now, and then put it back into the furnace which I haven't cooled down yet, and put it back in there, pump steam through it for about 10 or 15 minutes to grow back that oxide. Looks like I actually overshot the gate dielectric layer that we were shooting for, I'll flip to the back of the wafer just so that you can see the color easier because it's unpolished, so that's the shade of blue, so that puts us right here on the colour chart which is just above 1000A, and we were going for about 500 or 600A, so I checked my furnace and I actually left it on too hot, and it went up to 1400 degrees C, and that's where oxidation happened a lot faster than wanted, and thats going to mean that the treshold voltage to turn this device on is going to be much higher than I originally wanted it to be, because this region for a gate oxide is very thick, we'll see how it works.

So the next steps I won't show you because its redundant, but I'm going to use masks to make some openings in the drain and source areas, on this specific device I made the gate a little bit too wide on this one here, so I'm not going to have much room, but I'm going to create these openings in the SiO2 layer, and then I'm going to use silver conductive epoxy and I'm going to put a big layer of that on the gate, that covers most of the surface area of the gate, so that we have 2 nice big parallel surfaces for that electric field to be induced on, and then I'll make the drain and source connections, and then on the back of the wafer I'm going to etch through the oxide that we just grew, because the oxide grows everywhere, not just on the top layer, we have an equal amount of oxide on the back, I'm going to make an opening for the body or substrate connection, like I said, that gets tied in with the source of the device.

OK, super quick NMOS insulated gate field effect transistor test, multimeter measuring drain source resistance, and I have a bench power supply set to 18V, and as I connect the power supply that puts positive voltage onto the gate, you'll see there's a lot of leakage current, the drain-source resistance