Thermal oxidation

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"In microfabrication, thermal oxidation is a way to produce a thin layer of oxide (usually silicon dioxide) on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The rate of oxide growth is often predicted by the Deal-Grove model.[1] Thermal oxidation may be applied to different materials, but this article will only consider oxidation of silicon substrates to produce silicon dioxide." - Wikipedia

From Sam's "Semiconductor Fabrication Basics Background Theory" video: "OK the first topic that I want to go in more detail about is oxidation, so I talked about this a bit before, this is the growth of an oxide layer like SiO2 on the wafer and it is used for a lot of things, its extremely useful for passivation so for a protection layer, its a hydrophilic layer and bare silicon is hydrophobic so if you want to spin coat a chemical on to this such as a dopant chemical you want the silicon to be hydrophilic and it helps to have a very very thin oxide layer that you grow onto it and that will allow the water-based dopant to spin onto it easier, and its so thin it doesn't act as a dopant barrier. When you do a RCA clean steps 1 and 2 it actually leaves a very thin SiO2 passivation layer behind, so hydrophilic is very useful however when you're spinning photo-resist onto it you want a hydrophobic surface, you want to get rid of all the water on there, so not so very good for photo-resist.

Second thing, dopant barrier, so in the previous drawings I showed you about the MOSFET fabrication we used the SiO2 layer and then etch a pattern into it and then that pattern will prevent the phosphorous atoms from diffusing into the wafer in those spots, although P atoms do diffuse through the glass and the glass will become lightly doped its much slower than the diffusion through the silicon wafer so the dopants are effectively blocked by the SiO2

And then the last 2 uses: Surface dielectric and device dielectric and this is the use in MOSFETs because the gate or any device that makes a capacitor onto a piece of silicon is using it in this manner where capacitor is basically 2 parallel plates and this is the dielectric that separates those 2 plates. Why SiO2? Well, it's easy to work with, it can be grown thermally which is very nice, one of the main goals of fabrication plants is to cut down the thermal budget so a lot of times thermal oxidation is only used in a very very large high production area when they can keep their furnaces up 24/7 and keep feeding wafers into them, at low volume runs the thermal budget starts to become overwhelming. Another reason why SiO2 is used is because its thermal expansion characteristics are very similar to that of silicon so as you put the wafer in and out of furnaces in different steps as the wafer expands and contracts the SiO2 passivation layers will expand and contract at a similar rate so that when you pull them back out of the oven nothing gets cracked or stretched and all of your CD (Critical Dimensions) stay very much the same, its not going to be perfect but its better than other passivation layers. Thermal oxidation basically means you take the wafer and put it in a really hot oven and the SiO2 will grow onto that naturally which is very nice. There's 2 methods: dry and wet. Wet is much much much faster for a couple of reasons but to know that you have to understand the mechanisms first, we'll get there. This is what's going on for dry oxidation. We're just using the ambient Oxygen O2 in the air and then that comes in contact with the silicon and this should be over a lot of heat over 1200 degrees C it starts around 900 deg C 1200 deg C is really where you want to be if you are building an oxide and that forms SiO2 so -I'll talk about the graph in a second- so a few different thicknesses here it can range normally between a 100 and 5000A is where your practical limits are but this term here saying that gate oxides are around 150A thats actually not quite true anymore we are getting at smaller and smaller and the advantage of thinning out that gate oxide is giving us a lower threshold voltage on field effect devices which is great but it gives us more and more leakage so its kind of coming to equilibrium here where we do not want to get the gate oxides much smaller, and I believe -Im not too sure about this- but I believe the aspect ratio between gate length to gate thickness is about 9, I think, Im not too sure about that, so the thinnest gates are used for tunneling devices because you'll experience quantum tunneling at these very very thin gate oxides and thats part of the reason why these very thin gate oxides on MOSFETs they experience leakage because of the tunneling effect, as we get thicker than that they are used for pad oxides on more complicated devices [for LOCOS processing], passivation is a thick layer, but the thickest layer of SiO2 that will be used is for field oxides, its called field oxides not only because they are dopant barriers, all of these are for the most part, but because it blocks electric fields, its too thick to create an electric field under most conditions, so field oxides are not used for gate oxides because they are just too thick, and gate oxides rely on the fact that the oxide can be used to create electric fields and store charge in it but field oxides are too thick and we use that to our advantage when fabricating devices because it allows us to insulate multiple FET devices and grow more metalization layers and such onto a wafer.

Now let's understand the growth mechanism real quick, so with any thermal oxidation for the oxidation to take place, the oxygen O2 molecules have to come in contact with the silicon, and at first when you have a bare silicon wafer and you stick it in the oven thats great it happens right away you know you got this oxygen plentiful and you got the silicon wafer, but then as soon as you have the first layer of silicon dioxide grow onto that wafer all the sudden you have this layer thats blocking the silicon wafer underneath from the oxygen in the air so the rate will slow down, because like I said the reaction can't take place if the oxygen molecules are not in direct contact with the silicon, now we have this SiO2 layer in between them, so for the reaction to continue, either the silicon atoms have to diffuse up through the SiO2 to get to the oxygen, or the oxygen has to diffuse down in the SiO2 to get to the silicon wafer underneath and thats what happens with thermal oxidation, so initially this is called the linear growth stage, and its defined by linear growth constant B/A times time t, and that's right here in the graph here, that happens quite quickly and quite linearly, but then right here we get into the parabolic stage and its on the graph basically an inverse slanted parabola and thats due to that first SiO2 layer growing so that the O2 molecules are no longer in direct contact with the silicon and they have to diffuse all the way through that SiO2 layer and it takes a little bit of time to do so, so that's why we get this parabolic growth area here, and that can be kind of mitigated when we get to higher and higher temperatures. So at 950C this is going to be a more pronounced parabolic growth and then at 1200C its gonna be a little bit more linear a little bit better, but to help that problem even more than just raising the temperature, we do wet oxidation, and instead of using ambient O2 atmosphere we pump steam or water vapor into the furnace, and this cuts down the time dramatically to do so. Initially the linear growth linear is not changed much, but it will help this parabolic growth region immensely, and thats because when we're dealing with dry oxidation we're waiting for this big O2 molecule to diffuse through an already formed SiO2 layer, but with wet oxidation we're starting with Si + water and thats gonna yield SiO2 + H2 gas but since we are dealing with this water vapor it's actually a hydroxyl ion and it's smaller and will actually diffuse through SiO2 much much quicker than this O2 molecule, and that allows the parabolic growth region to be subdued and mitigated more, so we have more of a linear region throughout, and that's why wet oxidation is really the way to go, especially if you are doing this at home and you don't want to wait 24 hours to grow a field oxide, you can speed things up a lot by doing wet oxidation. But let's look at the downsides real quick. A very big goal of semiconductor fabs everywhere is to decrease the use of steps that involve liquids. We want to get everything so that all of these steps are done with gas sources, because gases are very pure and easy to maintain pure, so if we are just feeding this water even if its high quality deionized distilled water into the chamber and it becomes water vapor, there's a lot of opportunities for impurities to get in there, and the SiO2 film that is grown will not be as nice and as pure and as uniform when we do wet oxidation, the nicest film is with dry oxidation. Also semiconducting devices generally decrease in performance as they're exposed to more and more oxygen throughout all of the thermal steps, so if we can limit the amount of oxygen that they are exposed to that's better generally, it's mainly in diffusion steps where thats critical. But the dry oxidation although slower and more expensive because these furnaces have to be up higher and for longer, but it does give you a much nicer oxide, now this is only an issue when we are talking about things like gate oxides, that are very small, thin, precise and can't have a single pinhole on them. Because if we have a pinhole on the gate oxide, its no longer an insulating gate device, your electric field will be all screwy and the device characteristics will basically be garbage, so dry oxidation is a very good method for making gate oxides.

OK, let's continue talking about oxidation. So one major thing that influences the rate of oxidation is the crystal orientation of the wafer that you are growing it onto. For example <111> orientation wafers have a higher packing density, they have more silicon atoms per unit volume [? area I think] so the rate of growth will be a lot faster on <111> wafers, and field effect devices are fabricated on <100> wafers so that means some of the thermal steps are slower for making field effect devices as opposed to MEMS and bipolar devices. Oxide layers that are grown over highly doped phosphorous regions are less dense, this is very important, they also etch faster thats because they are grown faster, up to five times the growth rate which is incredible so you have to be very careful of this when you are planning out oxide growth and etching steps, this also leads to higher undercutting and lots of other problems, so you think "oh!" you know "faster rate!" but sometimes thats an issue.

When we have N type regions an effect called pile-up happens, and the reverse happens with P type "depletion", this is because phosphorous, an N type dopant, has a higher solubility in silicon than it does in SiO2. As the SiO2 layer grows, we talked about earlier how it grows not only above the surface of the wafer, but also into the wafer itself, because the oxygen or hydroxyl ions are diffusing into the wafer surface, so this oxide layer grows on top of the wafer and into the wafer. As it grows into the wafer the advancing SiO2 layer, literally pushes the N type dopant atoms further and further into the wafer, and they remain at the interface between the SiO2 and the silicon, so thats pile-up. And then the reverse happens for P-type dopants, where they're actually drawn out of the wafer so both of these you have to be very careful about when you are designing a process because they can dramatically affect your dopant distribution. Another thing that affects rate is the presence of hydrochloric acid HCl, and there's actually some methods of oxidation -cooling added oxidation- that actually uses to increase the rate overall and this could also introduce a whole lot of mobile ionic contaminants and other stuff. Another thing you have to be very careful about are differential rates, because we talked about earlier the difference between the linear and parabolic growth region. So if you have a wafer, here as an example these are the steps to make a FET, some regions of SiO2 are thicker than other regions let's just say this region here is below 500A, and this one is about 2000A. this means when we put this back in the furnace to add more, this will be in the linear growth stage and this will be in the parabolic growth region, this thing will grow faster than that. So you may think "Oh! well if I have a growth rate of 1000A per hour, I put this wafer in the oven and if I take it out after one hour, everything will be a 1000A thicker!" that is far from what will actually happen, you will have a lot of variations in rates all across your wafer, because each oxide is in varying stages of this growth and thats even more expanded on the non-uniformity of it due to uneven heating while its in the furnace so theres a lot of issues there and thats partially where CMP (chemical mechanical planarization) will come into play, another extremely complicated topic, that is outside the scope of this video. Anyway you have to be careful about differential oxide growth rates. Some other processes other than this thermal oxide growth: I'm not gonna over them, but it's worth mentioning theres rapid thermal processes, theres high pressure oxidation which gets rid of a lot of the issues with thermal oxidation and then theres anodic oxidation, which I try theres a video elsewhere on my youtube channel, the problem is it involves an aqueous solution of potassium hydroxide or potassium nitrate or something, and thats very dirty, its hard to control contaminants in liquid solution, thats why a lot of semiconductor processes deal only with gases. So its very simple, basically just passing a current through - you got your silicon wafer immersed in this aqueous solution and thats connected to the positive of a current supply I use about a 100V DC on mine hence the name anodic oxidation, and then the negative just goes to the solution as a whole. And this is done at room temperature atmospheric pressure."

http://sam.zeloof.xyz/silicon-wafer-pics-thermal-sio2-growth-500nm/


Thermal Oxide Growth Calc[edit]

Calc Link


Types of Furnaces[edit]

Optimally, a tube furnace with quartz tube should be used for these processes. I bought a 1" Lindberg Tube furnace. The furnace must be capable up temperatures around 1000c. My quartz tube was custom made by Greatglass. If you want to accelerate the growth rate you can find create ways of pumping steam into the furnace. Before I bought the tube furnace, I did all my doping and oxide growth with a very dirty box/pottery type furnace that came from a dentist's. These are far from ideal because they are lined with insulation rather than quartz so you will have tons of impurities, however it worked well enough for me to make basic devices so it is a good starting place for someone looking to start a home chip lab.